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 * Copyright 2021 Google Inc.
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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#ifndef __ARCH_SPARC_PSEUDO_INST_ABI_HH__
#define __ARCH_SPARC_PSEUDO_INST_ABI_HH__

#include "arch/sparc/regs/int.hh"
#include "cpu/thread_context.hh"
#include "sim/guest_abi.hh"
#include "sim/pseudo_inst.hh"

namespace gem5
{

struct SparcPseudoInstABI
{
    using State = int;
};

namespace guest_abi
{

template <typename T>
struct Result<SparcPseudoInstABI, T>
{
    static void
    store(ThreadContext *tc, const T &ret)
    {
        // This assumes that all pseudo ops have their return value set
        // by the pseudo op instruction. This may need to be revisited if we
        // modify the pseudo op ABI in util/m5/m5op_x86.S
        tc->setReg(SparcISA::int_reg::O0, ret);
    }
};

template <>
struct Argument<SparcPseudoInstABI, uint64_t>
{
    static uint64_t
    get(ThreadContext *tc, SparcPseudoInstABI::State &state)
    {
        panic_if(state >= 6, "Too many psuedo inst arguments.");
        return tc->getReg(SparcISA::int_reg::o(state++));
    }
};

template <>
struct Argument<SparcPseudoInstABI, pseudo_inst::GuestAddr>
{
    using Arg = pseudo_inst::GuestAddr;

    static Arg
    get(ThreadContext *tc, SparcPseudoInstABI::State &state)
    {
        panic_if(state >= 6, "Too many psuedo inst arguments.");
        return (Arg)tc->getReg(SparcISA::int_reg::o(state++));
    }
};

} // namespace guest_abi
} // namespace gem5

#endif // __ARCH_SPARC_PSEUDO_INST_ABI_HH__
